The present invention relates generally to the field of error control, and more particularly to the field of error detecting and correcting codes.
Error control is known. Error control is the detection and/or correction of data errors to ensure reliable data storage and/or delivery. Errors can occur due to a number of reasons, including, for example, unreliable storage hardware, unreliable communication channels, and/or channel noise such as background radiation. Error detection allows for the detecting of such errors, while error correction enables reconstruction of the original data to correct the errors.
One known error control scheme is the use of parity bits. A parity bit is a bit that is added to a group of source bits to ensure that the number of set bits (that is, bits with value 1) in the outcome is even or odd. Parity bits can be used to detect one or any other odd number (for example, three, five, etc.) of errors in the output. However, an even number of error-including bits will make the parity bit appear correct even though the data is erroneous. Parity bits are typically used in situations where an operation can be repeated in case of difficulty, where simply detecting the error is helpful.
Another known error control scheme is the use of error-correcting codes (or ECC). ECC are groups of bits that are added to source bits and are usable for both error detection and error correction. ECC typically accomplish error detection and correction by adding redundancy to the source bits using an algorithm. The redundant bits in ECC may, for example, be a complex function of many original source bits. ECC are commonly used in computers where data corruption cannot be tolerated under any circumstances, such as, for example, scientific or financial computing.